1. Field of the Invention
The present invention relates to a semiconductor memory, and more specifically to a static semiconductor memory which includes flip-flop circuit type memory cells with driving n-channel transistors and which is suitable to be incorporated into an application-specific integrated circuit.
2. Description of Related Art
Referring to FIG. 1, there is a partial circuit diagram of a conventional static semiconductor integrated circuit memory composed of flip-flop circuit type memory cells with driving n-channel transistors and arranged in the form of a matrix (first prior art example).
The shown conventional static semiconductor integrated circuit memory includes a number of memory cell columns, but only one memory cell column is shown for simplification of drawing since the memory cell columns have the same construction. The shown memory cell column includes a number of memory cells MC1 to MCm, but only two memory cells MC1 and MCm are shown for simplification of drawing since the memory cells have the same construction.
Each memory cell includes a pair of source-grounded driving n-channel MOSFET (met-al-oxide-semiconductor field effect transistor) transistors Q1 and Q2 each having a gate connected to a drain of the other driving transistor, and another pair of p-channel MOSFET transistors Q3 and Q4 having their source connected to a high voltage supply potential Vcc, their drain connected to the drain of the transistors Q1 and Q2, respectively, and their gate connected to the gate of the transistors Q1 and Q2, respectively. With this interconnection, CMOS (complementary MOS) flip-flop circuits are formed with each of the p-channel MOS transistors Q3 and Q4 as a load.
The memory cell further includes a switching n-channel transistor Q5 having a source and-.a drain, one of which is connected to the drains of the transistors Q1 and Q3, and another switching n-channel transistor Q6 having a source and a drain, one of which is connected to the drains of the transistors Q2 and Q4.
The shown conventional static semiconductor integrated circuit memory further includes a plurality of word lines WL1 to WLm provided for the memory cells included in each memory cell column, respectively, one for one. In addition, one pair of bit lines BL1 and BL2 is provided for each one of the memory cell columns, for transferring a pair of complementary binary data. Each of the word lines WL1 to WLm is connected to a gate of the switching transistors Q5 and Q6 of a corresponding memory cell of each memory cell column. One of the pair of bit lines BL1 is connected to the other of the source and the drain of the switching transistor Q5 of all the memory cells included in the corresponding memory cell column, and the other of the pair of bit lines BL2 is connected to the other of f source and the drain of the switching transistor Q6 of all the memory cells included in the same corresponding memory cell column. With this arrangement, if one of the word lines WL1 to WLm is activated to a selection level, the switching transistors Q5 and Q6 of the memory cell connected to the word line activated to the selection level are turned on, namely, the memory cell connected to the word line activated to the selection level is selected, so that a complementary data can be written through the pair of complementary bit lines BL1 and BL2 into the flip-flop circuit of the selected memory cell, or can read out from the flip-flop circuit of the selected memory cell through the pair of complementary bit lines BL1 and BL2.
Furthermore, the shown conventional static semiconductor integrated circuit memory includes a sense amplifier 1 having a first two-input NAND gate G1 having a first input connected to the bit line BL1, and a second two-input NAND gate G2 having a first input connected to the bit line BL2, a second input connected to an output of the first NAND gate G1 and an output connected to a second input of the first NAND gate G1, so that a flip-flop circuit is formed of the two NAND gates G1 and G2. An inverter IV1 is also provided, which has an input connected to the output of the NAND gate G1 and an output connected to an output terminal DO. With this arrangement, the sense amplifier 1 is formed to sense and amplify a voltage difference between the pair of complementary bit lines BL1 and BL2.
In the above mentioned conventional semiconductor memory, when data is read from the selected memory cell, since the bit lines BL1 and BL2 are connected to a number of memory cells MC1 to MCm and itself have a long wiring length, each of the bit lines BL1 and BL2 constitutes a large load, so that a level transition time of the bit lines BL1 and BL2 becomes long. In addition, generally, since a p-channel MOS transistor has a current drive capacity smaller than that of an n-channel MOS transistor because of difference in conductivity type of the impurity-diffused layers, the bit lines BL.sub.1 and BL.sub.2 relatively quickly transit in from a high level to a low level by action of the driving n-channel MOS transistors Q1 and Q2, but the bit lines BL1 and BL2 relatively remarkably slowly transit in from the low level to the high level by action of the load p-channel MOS transistors Q3 and Q4. This problem will similarly occur even if the load circuit of the memory cells MC1 to MCm is constituted of resistors in place of the p-channel MOS transistors Q3 and Q4.
In order to overcome this problem, for example, Japanese Patent Application Laid-open Publication Nos. JP-A-63-009095 and JP-A-4-102294 proposed an improved semiconductor memory in which each bit line is precharged to an intermediate level between a high level and a low level. In this approach, a reading operation can be started until a precharge operation is completed, and therefore, this precharge operation period becomes a hindrance in improving the operation speed.
In the meanwhile, in a semiconductor memory used in an application specific integrated circuit (abbreviated to an "ASIC"), it is conventional practice to connect a pull-up circuit to each of the bit lines in order to quicken the potential elevation of the bit line.
Referring to FIG. 2, there is a partial circuit diagram of a second example of the conventional static semiconductor integrated circuit memory having the pull-up circuit (second prior art example). In FIG. 2, elements similar to those shown in FIG. 1 are given the same Reference Numerals and explanation thereof will be omitted for simplification of description. As seen from comparison between FIGS. 1 and 2, the second prior art example is featured by pull-up circuits 2 and 2X additionally connected to the bit lines BL1 and BL2, respectively, in the first prior art example shown in FIG. 1.
The pull-up circuit 2 includes a p-channel transistor Q21 having a source connected to the high voltage supply potential Vcc, a drain connected to the bit line BL1, and a gate connected to the bit line BL2. The pull-up circuit 2X includes a p-channel transistor Q22 having a source connected to the high voltage supply potential Vcc, a drain connected to the bit line BL2, and a gate connected to the bit line BL1.
Operation of this semiconductor memory of the second prior art example will be described with a waveform diagram of FIG. 3.
When the bit line BL1 changes from a low level to a high level, the bit line BL2 changes from the high level to the low level. In this process, when the potential of the bit line BL2 becomes lower than a threshold Vta of the transistor Q21 of the pull-up circuit 2, the transistor Q21 is turned on, so that the high voltage supply potential Vcc is supplied through the turned-on transistor Q21 to the bit line BL1. As a result, the time required for the bit line BL1 to reach the high level (high voltage supply potential Vcc) is shortened. In FIG. 3, the dotted line shows the first prior art example which does not have the pull-up circuit 2.
On the other hand, the transistor Q22 of the pull-up circuit 2X is in an on condition at an initial stage of the above mentioned level transiting process, but since the transistor Q2 of the memory cells MC1 to MCm has the current drive capacity far larger than that of the transistor Q22, influence of the on condition of the transistor Q22 is very small.
In this second prior art example, for example, a specific data reading time was 2.9 ns for a low level data and 4.2 ns for a high level data.
Therefore, the difference between the high level data reading time and the low level data treading time was greatly improved in the second prior art example, however, the high level data reading time is still longer than the low level data reading time at an non-negligible degree, with the result that the overall reading speed is still low.
In order to overcome this problem, it may be considered to lower a pull-up potential, but to the contrary, adverse influences such as noises occur to the sense amplifier.